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19-2624; Rev 0; 10/02
10Gbps 1:16 Deserializer with Clock Recovery
General Description
The MAX3953 is a 9.953Gbps/10.3125Gbps 1:16 deserializer with clock recovery for 10Gbps Ethernet and OC192 SONET applications. The integrated phaselocked loop (PLL) recovers a clock from the serial data input, and the data is then retimed and demultiplexed into 16 parallel LVDS outputs. Using Maxim's SiGe bipolar process, the MAX3953 can achieve 0.75UI of high-frequency jitter tolerance comprised of 0.50UI of deterministic jitter and 0.25UI of random jitter. The MAX3953 includes TTL-compatible loss-of-lock (LOL) and sync-error (SYNC_ERR) indicators that allow the user to verify that the part has locked on to incoming data. In case the incoming data becomes invalid, a clock holdover function is provided to maintain a valid reference clock to the upstream device. For proper operation, a reference clock of baud rate/64 or baud rate/16 is required. The MAX3953 operates from a single +3.3V power supply and typically dissipates 1.5W. The operating temperature range is from 0C to +85C. The MAX3953 is available in a 68-pin QFN package.
Features
o Serial Data Rate: 9.953Gbps/10.3125Gbps o Clock Recovery with 1:16 Demultiplexer o 0.75UIP-P High-Frequency Jitter Tolerance o 16-Bit Parallel LVDS Output o OIF-Compliant Parallel Interface o Loss-of-Lock (LOL) Indicator o Differential Input Range: 100mVP-P to 1.2VP-P o Clock Holdover o Reference Clock: Baud Rate/64 or Baud Rate/16 o Temperature Range: 0C to +85C o 10mm 10mm 68-Pin QFN Package
MAX3953
Ordering Information
PART MAX3953UGK TEMP RANGE 0oC to +85oC PIN-PACKAGE 68 QFN (10mm x 10mm)
Applications
10Gbps Ethernet LAN 10Gbps Ethernet WAN Add/Drop Multiplexers Digital Cross-Connects
Pin Configuration and Functional Diagram appear at end of data sheet.
Typical Operating Circuit
+3.3V
RATESET -3.3V 0.047F FIL 0.01F 161MHz CLOCK 0.1F 0.1F TIA LIMITING AMP 0.1F SDI+ SDI0.1F LOS_IN GND 0.1F REFCLK+ 100* REFCLK-
VCC
PDOI5+ 100* PDOI5PDO0+
VCC
OVERHEAD 100* TERMINATION
MAX3953
PDO0PCLK0+ 100* PCLK0LOL SYNC_ERR CLKSEL
MAX3970 0.1F
MAX3971A
REFSET
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50.
________________________________________________________________ Maxim Integrated Products
1
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10Gbps 1:16 Deserializer with Clock Recovery MAX3953
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ............................................-0.5V to +5.0V Input Voltage Levels (SDI+, SDI-) .................................(VCC - 1.0V) to (VCC + 0.5V) LVDS Output Voltage Levels (PDO[15..0], PCLKO+, PCLKO-) .........-0.5V to (VCC + 0.5V) Voltage at LOL, SYNC_ERR, RATESET, CLKSEL, REFCLK+, REFCLK-, REFSET, LOS_IN, FIL ............-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = 85C) 68-Lead QFN (derate 30.3mW/C above +85C) ............2.5W Operating Temperature Range.............................. 0C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C Processing Temperature (die) .........................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER POWER SUPPLY Supply Current Differential Input Voltage Common-Mode Input Range Input Termination to VCC Differential Input Voltage LVPECL Input High Voltage LVPECL Input Low Voltage LVPECL Input Bias Voltage Differential Input Impedance OUTPUT SPECIFICATION (PDO[15..0], PCLKO) LVDS Output High Voltage LVDS Output Low Voltage LVDS Differential Output Voltage LVDS Change in Magnitude of Differential Output for Complementary States LVDS Offset Output Voltage LVDS Change in Magnitude of Output Offset Voltage for Complementary States LVDS Differential Output Impedance LVDS Output Current Short together or short to GND VOH VOL VOD VOD VOD VOD 1.125 0.925 250 400 25 1.275 25 1.475 V V mV mV V mV RIN AC-coupled or DC-coupled input ICC VID AC-coupled or DC-coupled input DC-coupled 100 VCC 0.3 40 300 VCC 1.16 VCC 1.81 VCC 1.3 2.6 50 476 580 1200 VCC 60 1600 VCC 0.88 VCC 1.48 mA mVP-P V mVP-P V V V k INPUT SPECIFICATION (SDI+, SDI-) Figure 1 SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE CLOCK INPUT (REFCLK+, REFCLK-) (Note 1)
80
140 20
mA
2
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10Gbps 1:16 Deserializer with Clock Recovery
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input Current LVTTL Output High Voltage LVTTL Output Low Voltage VOH VOL IOH = 20A IOL = 1mA SYMBOL VIH VIL -50 2.4 CONDITIONS MIN 2 0.8 +6 VCC 0.4 TYP MAX UNITS V V A V V LVTTL INPUT AND OUTPUT (CLKSEL, SYN_ERR, RATESET, LOS_IN, LOL, REFSET)
MAX3953
Note 1: Reference clock duty cycle can range from 30% to 70%.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at +3.3V and TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Serial Input Data Rate Sinusoidal Jitter Tolerance Tolerated Consecutive Identical Digits Input Return Loss Frequency Difference when PLL Indicates Out of Lock Frequency Difference when PLL Indicates In Lock LOL Assert Time PLL Acquisition Time Maximum PCLKO Deviation from REFCLK Output Clock to Data Delay Output Clock Duty Cycle tCLK-Q Figure 3 -150 45 50 No transitions at input, Figure 2 Valid transitions at input, Figure 2 SYMBOL CONDITIONS RATESET = GND RATESET = VCC f = 400kHz (Notes 3, 4) f = 4MHz (Note 3) Bit-error ratio (BER) = 10-12 f < 10GHz, differential f < 15GHz, differential f < 15GHz, common mode 1.5 0.15 2000 10 8 9 1000 500 30 100 100 2500 +150 55 ppm ppm s s ppm ps % dB MIN TYP 9.953 10.3125 MAX UNITS Gbps UIP-P Bits
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10Gbps 1:16 Deserializer with Clock Recovery MAX3953
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at +3.3V and TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Output Clock and Data Rise/Fall Time LVDS Differential Skew LVDS Channel-to-Channel Skew SYMBOL tR, tF tSKEW1 tSKEW2 20% to 80% Any differential pair PDO[15..0] CONDITIONS MIN 100 TYP MAX 250 50 100 UNITS ps ps ps
Note 2: Guaranteed by design and characterization for TA = 0C to +85C. Note 3: Measured with 0.45UIP-P deterministic jitter and 0.15UIP-P random jitter, on top of the specified sinusoidal jitter in a 231 - 1 PRBS pattern with a BER = 10-12. Note 4: The jitter tolerance exceeds IEEE 802.3AE specifications. The jitter tolerance outperforms the instrument's measurement capability.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
RECOVERED DATA AND CLOCK (0.3Gbps INPUT)
MAX3953 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX3953 toc02
BIT-ERROR RATIO vs. INPUT VOLTAGE
10-4 10-5 BIT-ERROR RATIO 10-6 10-7 10-8 10-9 10-10 10-11 10-12
MAX3953 toc03
600 570 540 SUPPLY CURRENT (mA) 510 480 450 420 390 360 330 300 0 20 40 60 80 +3.3V +3.0V +3.6V
10-3
CLOCK
DATA
500ps/div
100
18.0
18.5
19.0
19.5
20.0
20.5
21.0
TEMPERATURE (C)
INPUT VOLTAGE (mVP-P)
DIFFERENTIAL S11 vs. FREQUENCY
MAX3953 toc04
JITTER TOLERANCE
MAX3953 toc05
JITTER GENERATION vs. POWER-SUPPLY FREQUENCY
MAX3953 toc06
0 -10 -20 S11 (dB) -30 -40 -50 -60 0 5000 10,000 FREQUENCY (kHz) 15,000
10 SINUSOIDAL INPUT JITTER (UIP-P)
6 5 JITTER GENERATION (psRMS) 4 3 2 1 0 0 5000 10,000 15,000 20,000 100mVP-P SINUSOID ON VCC WIDEBAND JITTER GENERATION OF PCLKO AT 622MHz
1
0.1
10Gbps ETHERNET JITTER TOLERANCE MEASURED WITH 0.45UI DETERMINISTIC JITTER AND 0.15UI RANDOM JITTER 10 100 1000 10,000
0.01 20,000
25,000
JITTER FREQUENCY (kHz)
POWER-SUPPLY FREQUENCY (kHz)
4
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10Gbps 1:16 Deserializer with Clock Recovery
Pin Description
PIN 1, 4, 5, 6, 14, 17, 18, 34, 35, 51, 52, 60, 68 2 3 7 8, 11, 12, 13, 15, 16, 27, 42, 59, 66 9 10 19 NAME GND REFCLK+ REFCLKREFSET Ground Positive Reference Clock Input, LVPECL. Connect a baud rate/64 or baud rate/16 reference clock. Negative Reference Clock Input, LVPECL. Connect a baud rate/64 or baud rate/16 reference clock. Reference Clock Select Input, TTL. When the reference clock is baud rate/64, set REFSET to GND. When the reference clock is baud rate/16, set REFSET to VCC. +3.3V Supply Voltage Positive Serial Data Input, CML. 9.953Gbps/10.3125Gbps serial data stream. Negative Serial Data Input, CML. 9.953Gbps/10.3125Gbps serial data stream. Loss-of-Signal Input, TTL. The LOS_IN is an external input. Clock holdover is activated when LOS_IN is TTL low. Connect to VCC if LOS input is not available. See the Clock Holdover Mode section. Loss-of-Lock Indicator Output, TTL. LOL signals a TTL low when the VCO frequency is more than 1000ppm from the reference clock frequency. LOL signals a TTL high when the VCO frequency is within 500ppm of the reference clock frequency. See the Clock Holdover Mode section. Positive Parallel Clock Output, LVDS Negative Parallel Clock Output, LVDS FUNCTION
MAX3953
VCC SDI+ SDILOS_IN
20 21 22 23, 25, 28, 30, 32, 36, 38, 40, 43, 45, 47, 53, 55, 57, 61, 63 24, 26, 29, 31, 33, 37, 39, 41, 44, 46, 48, 54, 56, 58, 62, 64 49
LOL PCLKO+ PCLKOPDO15+ to PDO0+
Positive Parallel Data Outputs, LVDS
PDO15to PDO0-
Negative Parallel Data Outputs, LVDS
SYNC_ERR
Synchronization Error Output, TTL. SYNC_ERR is intended to drive CLKSEL for holdover mode. See the Clock Holdover Mode section. Output Clock Selector, TTL. CLKSEL is the control input for clock holdover. When CLKSEL = GND, PCLKO is derived from the input data. When CLKSEL = VCC, PCLKO is derived from the reference clock. Serial Data Rate Select Input, TTL. When the input serial data stream is 9.953Gbps, set RATESET to GND. When the input serial data stream is 10.312Gbps, set RATESET to VCC. PLL Loop Filter Capacitor Input. A capacitor between this pin and VCC sets the loop to zero. A 0.047F capacitor is recommended. Ground. This must be soldered to the circuit board ground for proper thermal and electrical performance. See the Layout Considerations section.
50
CLKSEL
65 67 EP
RATESET FIL Exposed Pad
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10Gbps 1:16 Deserializer with Clock Recovery MAX3953
Detailed Description
The MAX3953 deserializer with clock recovery converts 9.953Gbps/10.3125Gbps serial data into 16-bit wide, 622Mbps/644Mbps parallel data. The device combines a fully integrated phase-locked loop (PLL), TTL-compatible status monitors, input amplifier, data retiming block, 16-bit demultiplexer, clock dividers, and LVDS output buffers. The PLL consists of a phase/frequency detector (PFD), a loop filter, and voltage-controlled oscillator (VCO). The PLL recovers the serial clock from the input data stream and retimes the data. The demultiplexer generates a 16-bit-wide 622Mbps/644Mbps parallel data output. The MAX3953 is designed to deliver the best jitter performance by using differential signal architecture and low-noise design techniques.
Applications Information
Clock Holdover Mode
The clock holdover mode is designed to provide an accurate parallel clock in the event of a loss-of-lock (LOL) or loss-of-signal (LOS) condition. The activation of the holdover mode is controlled by the SYNC_ERR, LOS_IN, and CLKSEL pins. CLKSEL is an input signal used to select the VCO to lock on to the incoming data (SDI) or the reference clock (REFCLK). The architecture of the holdover mode is shown in Figure 4. Holdover mode is activated by connecting SYNC_ERR to CLKSEL.
Consecutive Identical Digits (CIDs)
The MAX3953 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 10-12. The CID tolerance is tested using a 213 - 1 pseudorandom bit stream (PRBS), substituting a long run of zeros to simulate worst case. A CID tolerance of greater than 2,000 bits is typical.
Input Amplifier
The serial data input (SDI) amplifier accepts differential input amplitudes from 100mVP-P to 1200mVP-P.
Phase-Frequency Detector
The digital phase-frequency detector (PFD) aids frequency acquisition during startup conditions. Depending on the polarity of the frequency input difference between REFCLK and the VCO clock, the PFD drives the VCO until the frequency difference is reduced to zero. False locking is eliminated by this digital phase-frequency detector. The data phase detector is optimized to achieve 0.75UI high-frequency jitter tolerance.
Exposed-Pad Package
The exposed pad, 68-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3953 and should be soldered to the circuit board for proper thermal and electrical performance. See Maxim Application Note HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for further information.
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. A 0.047F capacitor (CF) is required to set the PLL damping ratio. The loop filter output controls the on-chip VCO.
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3953 high-speed inputs and outputs. Power-supply decoupling should be placed as close to the VCC as possible. To reduce feed-through, isolate input signals from output signals.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is included in the MAX3953 frequency detector. A loss-of-lock condition is signaled with a TTL low. When the PLL is frequency locked, LOL switches to TTL high in approximately 56s. LOL signals a TTL low when the VCO frequency is more than 1000ppm from the reference clock frequency. LOL signals a TTL high when the VCO frequency is within 500ppm of the reference clock frequency.
Low-Voltage Differential Signal (LVDS) Outputs
The MAX3953 features LVDS outputs for interfacing with high-speed circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 500mVP-P to 800mVP-P differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity.
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10Gbps 1:16 Deserializer with Clock Recovery MAX3953
VCC 600mV VCC - 0.3V
50mV
231 - 1 PRBS INPUT DATA
231 - 1 PRBS
VCC - 0.6V (a) DC-COUPLED CML INPUT LOL ASSERT TIME VCC + 0.3V LOL OUTPUT 600mV VCC 50mV PLL ACQUISITION TIME
VCC - 0.3V (b) AC-COUPLED CML INPUT
Figure 1. Input Amplitude
Figure 2. LOL Assert and Acquisition Time
REFCLK
tCLK PCLK+ tCLK-Q PDO
VCO LOS_IN
PFD
LOL STATE MACHINE
LOL SYNC_ERR CLKSEL
REFCLK SDI PLL MAX3953
Figure 3. Timing Parameters
Figure 4. Clock Holdover Architecture
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10Gbps 1:16 Deserializer with Clock Recovery MAX3953
Functional Diagram
CLKSEL
LOL
SYNC_ERR
LOS_IN
TTL TTL TTL
TTL
HOLDOVER STATE MACHINE REFCLK+ PECL REFCLKPHASE AND FREQUENCY DETECTOR LOOP FILTER VCO DIV N
DIV 16
PCLKO+ LVDS PCLKOPDO15+ LVDS PDO15-
REFSET
TTL
16-BIT DEMULTIPLEXER Q SDI+ CML SDIMAX3953 D
PDO1+ LVDS PDO1PDO0+ LVDS PDO0-
FIL
8
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10Gbps 1:16 Deserializer with Clock Recovery
Pin Configuration
PDO0+ PDO1+ PDO2+ PDO3+ PDO3PDO4+ PDO0PDO1PDO2PDO4-
MAX3953
TOP VIEW
GND VCC
68
RATESET
GND
67 66 65 64
63 62 61 60 59 58 57 56 55 54 53 52 51 GND 50 CLKSEL 49 SYNC_ERR 48 PDO547 PDO5+ 46 PDO645 PDO6+ 44 PDO7-
GND REFCLK+ REFCLKGND GND GND REFSET VCC SDI+
1 2 3 4 5 6 7 8 9
MAX3953
GND
43 PDO7+ 42 VCC 41 PDO840 PDO8+ 39 PDO938 PDO9+ 37 PDO1036 PDO10+ 35 GND
SDI- 10 VCC 11 VCC 12 VCC 13 GND 14 VCC 15 VCC 16 GND 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
PCLKO+
LOL
PDO15+
PDO14+
VCC
FIL
PDO13+
PDO15-
PDO14-
PDO12+
PDO11+
PDO13-
PDO12-
PDO11-
LOS_IN
PCLKO-
GND
QFN*
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION.
GND
VCC
Chip Information
TRANSISTOR COUNT: 11,612 PROCESS: SiGe BIPOLAR
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10Gbps 1:16 Deserializer with Clock Recovery MAX3953
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
68L QFN, 10x10x09,EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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